1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and in particular to a semiconductor device having, as being provided on both surfaces of a leadframe, semiconductor chips each having a plurality of bonding pads.
2. Description of the Related Art
One known conventional semiconductor device is such as being described for example in Japanese Laid-Open Patent Publication No. H07-335826. The semiconductor device described in this document is shown in FIG. 12. The semiconductor device 800 have two semiconductor chips 8a, 8b disposed, as being rotationally shifted from each other, on both surfaces of a die pad 2 of a leadframe. This makes it possible to ease congestion of leads 3 and wires 9a, 9b in the peripheral portion, and to facilitate the fabrication.
Another semiconductor device described in Japanese Laid-Open Patent Publication No. H08-330508 is shown in FIGS. 13A and 13B. The semiconductor device 810 described in this document has two semiconductor chips 11D, 11E, disposed as being shifted from each other in a parallel or orthogonal manner, mounted on one surface of an island of a leadframe, wherein thus-shifted semiconductor chips 11D and 11E have a plurality of pads 13D and 13E, respectively, arranged in the peripheral portions of the top surfaces thereof.
Still another semiconductor device described in Japanese Laid-Open Patent Publication No. 2001-358285 is shown in FIG. 14. The semiconductor device 820 has, on both surfaces of an interconnection substrate 21, two semiconductor chip groups CH3(CH1), CH2(CH4), respectively, as being shifted from each other only in the horizontal, or linear direction. The interconnection substrate 21 has through-hole electrodes provided therein, by which the inner electrodes of the individual semiconductor chips CH1 and CH4 are connected with each other. In the semiconductor device 820, a plurality of external electrodes BP1 to BP14 of the semiconductor chip CH3 are electrically connected through bonding wires 23 to a plurality of bonding areas 22B on the interconnection substrate 21, and similarly in the semiconductor chip CH4, a plurality of external electrodes are electrically connected through the bonding wires to a plurality of bonding areas on the interconnection substrate 21.
The prior arts described in the above documents, however, gave no consideration on mounting of the chips on both surfaces of the island so as to avoid overlapping of the boding pads of the chips. Any semiconductor devices having the semiconductor chips mounted on both surfaces of the island portion, as being fabricated by the conventional methods of fabricating the semiconductor devices, may sometimes result in parallel overlapping, in a plan view, of the wires connecting the pads of the individual chips and the leads, so that any accidental omission of one of the wires has been very unlikely to be detected in manufacturing inspection based on X-ray transmission image or the like. This has been a causal factor of degradation in the fabrication reliability of semiconductor device.
The present invention was conceived after considering the above-described situations, and an object thereof to provide a semiconductor device having a good fabrication reliability, and a method of fabricating the same.